Research
Topological Qubits
Recently it has been predicted that two-dimensional planar Josephson junction can host of the so-called Majorana fermions. Most earlier proposals relied on nanowires which have been the main focus of Microsoft. Topological qubits are postulated to provide fault-tolerant computation at hardware level which sounds better than error correction using surface codes with a large overhead on number and performance of the superconducting qubits. The mainstream qubit hardware used at IBM and Google, called transmons, are based on superconducting qubits that have Josephson junctions at their core. By marrying the two technologies, one can use topological junctions in transmon architecture to achieve topological qubits. As a first step, we have recently shown using epitaxial Al/InAs Josephson junctions we can observe a clear transition between trivial and topological superconductivity. We are working toward fusion and braiding circuits.
Multi-gate Josephson Junctions
Gatemon: Tunable Qubits
In quantum computing architectures, an important factor is the tradeoff between the need to couple qubits to each other and to an external drive and the need to isolate qubits enough so that the information remains well protected. In the case of superconducting circuits, a popular approach is to work with fixed-frequency qubits so that the system can be kept in a configuration that is relatively insensitive to noise. However, the closely spaced energy levels associated with each qubit make fast, high-fidelity quantum control quite challenging as stronger driving typically causes leakage to higher energy states and thus larger errors. In order to mitigate this issue, our approach is to use qubits that can be rapidly tuned in and out of resonance with other qubits or circuit components so that the system can remain in a noise-resistant configuration as much as possible without limiting operation times. We use semiconductor-based Josephson junctions to realize tunable superconducting qubits, the so-called “gatemon” where the Josephson energy can be tuned with an applied electric field.
Epitaxial Superconductor on Semiconductor Heterostructures
Our group has developed a wafer-scale method for the epitaxial growth of thin films of Al on III-V compound heterostructures with atomically flat interfaces. The main challenge in interfacing superconductors and semiconductors is that they often belong to distinct classes of materials with very different crystal structure, lattice constants and melting points. Growth conditions must be carefully optimized and combined with the appropriate selection of metallic phases in order to suppress the strong tendency of island formation and film agglomeration during the growth. We have made the wafer list of our III-V MBE machine available here.