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Dr. Johann Knechtel

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Email: johann at nyu dot edu

Johann Knechtel is a Research Scientist with the Design for Excellence Lab, headed by Prof Ozgur Sinanoglu, in the Division of Engineering, at the New York University (NYU), Abu Dhabi, UAE. A more detailed biography can be found here.

Research Interests

Hardware Security, Electronic Design Automation (EDA), 3D Integration, Emerging Technologies

Open-Source Software

  • Various security-related software projects can be found at https://github.com/DfX-NYUAD
  • Corblivar is a simulated-annealing-based floorplanning suite for 3D ICs, with special emphasis on planning of large-scale interconnects, timing-driven voltage assignment, and analysis and mitigation of thermal side-channel leakage. See details and download at https://github.com/IFTE-EDA/Corblivar

Publications

Last updated Jan 02, 2023

Articles in Journals, Magazines

  1. L. Mankali, L. Alrahis, S. Patnaik, J. Knechtel, and O. Sinanoglu, “Titan: Security analysis of large-scale hardware obfuscation using graph neural networks,” IEEE Trans. Inf. Forens. Sec. (TIFS), vol. 18, pp. 304–318, 2022. DOI: 10.1109/TIFS.2022.3218429 (PDF)
  2. G. A. Chacon, C. Williams, J. Knechtel, O. Sinanoglu, and P. V. Gratz, “Hardware Trojan threats to cache coherence in modern 2.5D chiplet systems,” IEEE Comp. Arch. L. (LCA), vol. 21, no. 2, pp. 133–136, 2022. DOI: 10.1109/LCA.2022.3216820 (PDF)
  3. L. Alrahis, J. Knechtel, F. Klemme, H. Amrouch, and O. Sinanoglu, “GNN4REL: Graph neural networks for predicting circuit reliability degradation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD), vol. 41, no. 11, pp. 3826–3837, 2022. DOI: 10.1109/TCAD.2022.3197521 (PDF)
  4. N. Rangarajan, J. Knechtel, N. Limaye, O. Sinanoglu, and H. Amrouch, “A novel attack mode on advanced technology nodes exploiting transistor self-heating,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD), vol. 41, no. 11, pp. 4134–4144, 2022. DOI: 10.1109/TCAD.2022.3197496 (PDF)
  5. J. Knechtel, T. Ashraf, N. Fernengel, S. Patnaik, M. Nabeel, M. Ashraf, O. Sinanoglu, and H. Amrouch, “Design-time exploration of voltage switching against power analysis attacks in 14nm FinFET technology,” Integration, vol. 85, pp. 27–34, 2022, invited paper. DOI: 10.1016/j.vlsi.2022.02.006 (PDF)
  6. A. Sengupta, M. Nabeel, J. Knechtel, and O. Sinanoglu, “A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL,” in MDPI Cryptography, vol. 6, No. 2, 2022 (DOI: 10.3390/cryptography6020022) (Link)
  7. N. Rangarajan, J. Knechtel, D. Rajasekharan, and O. Sinanoglu, “SuperVAULT: Superparamagnetic volatile auxiliary tamper-proof storage,” IEEE Emb. Sys. L. (ESL), vol. 14, No. 2, pp. 103–106, 2021 (DOI : 10.1109/LES.2021.3127682) (PDF)
  8. L. Alrahis, A. Sengupta, J. Knechtel, S. Patnaik, H. Saleh, B. Mohammad, M. Al-Qutayri, and O. Sinanoglu, “GNN-RE: Graph neural networks for reverse engineering of gate-level netlists,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD), 2021 (DOI: 10.1109/TCAD.2021.3110807) (PDF)
  9. L. Alrahis, S. Patnaik, J. Knechtel, H. Saleh, B. Mohammad, M. Al-Qutayri, and O. Sinanoglu, “UNSAIL: Thwarting oracle-less machine learning attacks on logic locking,” IEEE Trans. Inf. Forens. Sec. (TIFS), 2021 (DOI: 10.1109/TIFS.2021.3057576) (PDF)
  10. S. Patnaik, M. Ashraf, H. Li, J. Knechtel, and O. Sinanoglu, “Concerted wire lifting: Enabling secure and cost-effective split manufacturing,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD), 2021 (DOI : 10.1109/TCAD.2021.3056379) (PDF)
  11. S. Rai, S. Patnaik, P. Nath, A. Rupani, J. Knechtel, O. Sinanoglu, and A. Kumar, “Security promises and vulnerabilities in emerging reconfigurable nanotechnology-based circuits,” IEEE Trans. Emerg. Topics Comput. (TETC), 2020 (DOI: 10.1109/TETC.2020.3039375) (PDF)
  12. H. Li, S. Patnaik, M. Ashraf, H. Yang, J. Knechtel, B. Yu, O. Sinanoglu, and E. F. Y. Young, “Deep learning analysis for split manufactured layouts with routing perturbation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD), 2020 (DOI: 10.1109/TCAD.2020.3037297) (PDF)
  13. H. Park, J. Kim, V. C. K. Chekuri, M. A. Dolatsara, M. Nabeel, A. Bojesomo, S. Patnaik, O. Sinanoglu, M. Swaminathan, S. Mukhopadhyay, J. Knechtel, and S. K. Lim, “Design flow for active interposer-based 2.5D ICs and study of RISC-V architecture with secure NoC,” IEEE Trans. Compon., Pack., Manuf. Tech. (TCPMT), vol. 10, No. 12, pp. 2047–2060, 2020 (DOI: 10.1109/TCPMT.2020.3033136) (PDF)
  14. M. Nabeel, M. Ashraf, S. Patnaik, V. Soteriou, O. Sinanoglu, and J. Knechtel, “2.5D root of trust: Secure system-level integration of untrusted chiplets,” IEEE Trans. Comput. (TC), vol. 69, No. 11, pp. 1611–1625, 2020 (DOI: 10.1109/TC.2020.3020777) (PDF) Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou.
  15. J. Knechtel, S. Patnaik, M. Nabeel, M. Ashraf, Y. S. Chauhan, J. Henkel, O. Sinanoglu, and H. Amrouch, “Power side-channel attacks in negative capacitance transistor,” IEEE Micro, vol. 40, No. 6, pp. 74–84, 2020 (DOI: 10.1109/MM.2020.3005883) (PDF) J. Knechtel, S. Patnaik, and M. Nabeel contributed equally.
  16. N. Rangarajan, S. Patnaik, J. Knechtel, R. Karri, O. Sinanoglu, and S. Rakheja, “Opening the doors to dynamic camouflaging: Harnessing the power of polymorphic devices,” IEEE Trans. Emerg. Topics Comput. (TETC), 2020 (DOI: 10.1109/TETC.2020.2991134) (PDF) S. Patnaik and N. Rangarajan contributed equally.
  17. N. Rangarajan, S. Patnaik, J. Knechtel, O. Sinanoglu, and S. Rakheja, “SMART: A secure magnetoelectric antiferromagnet-based tamper-proof non-volatile memory,” IEEE Access, vol. 8, pp. 76 130–76 142, 1 2020 (DOI: 10.1109/ACCESS.2020.2988889) (PDF)
  18. S. Patnaik, M. Ashraf, O. Sinanoglu, and J. Knechtel, “Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, No. 12, pp. 4466–4481, 2020 (DOI: 10.1109/TCAD.2020.2981034) (PDF)
  19. S. Patnaik, M. Ashraf, O. Sinanoglu, and J. Knechtel, “A modern approach to IP protection and trojan prevention: Split manufacturing for 3D ICs and obfuscation of vertical interconnects,” in IEEE Trans. Emerging Topics in Computing (TETC), 2019 (DOI: 10.1109/TETC.2019.2933572) (PDF)
  20. J. Knechtel, J. Gosciniak, A. Bojesomo, S. Patnaik, O. Sinanoglu, and M. Rasras, “Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators,” in IEEE/OSA J. Lightwave Technology (JLT), Vol. 37, No. 15, pp. 3805-3814, 2019, (DOI: 10.1109/JLT.2019.2920949) (PDF) J. Knechtel and J. Gosciniak contributed equally.
  21. S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, and S. Rakheja, “Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, No. 8, pp. 1591–
    1606, 2019 (DOI: 10.1109/TCAD.2019.2917856) (PDF) S. Patnaik, N. Rangarajan, and J. Knechtel contributed equally.
  22. N. Rangarajan, S. Patnaik, J. Knechtel, O. Sinanoglu, and S. Rakheja, “Spin-based Reconfigurable Logic for Power- and Area-Efficient Applications,” in IEEE Design & Test (DT), Vol. 36, No. 3, pp. 22-30, 2019 (DOI: MDAT.2019.2895021) (PDF) N. Rangarajan and S. Patnaik contributed equally.
  23. J. Knechtel, J. Lienig, and I. A. M. Elfadel, “Multi-Objective 3D Floorplanning with Integrated Voltage Assignment,” in ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 23, No. 2, pp. 22:1-22:27, 2017 (DOI: 10.1145/3149817) (PDF)
  24. A. Henning-Knechtel, J. Knechtel, M. Magzoub, “DNA-assisted oligomerization of pore-forming toxin monomers into precisely-controlled protein channels,” in Nucleic Acids Research (NAR), Vol. 45, No. 21, pp. 12057-12068, 2017 (DOI: 10.1093/nar/gkx990) (PDF) breakthrough article and cover feature
  25. J. Knechtel, O. Sinanoglu, I. A. M. Elfadel, J. Lienig, and C. C. N. Sze, “Large-Scale 3D Chips: Challenges and Solution for Design Automation, Testing, and Trustworthy Integration,” in IPSJ Trans. on System LSI Design Methodology (TSLDM), Vol. 10, pp. 45-62, 2017 (DOI: 10.2197/ipsjtsldm.10.45) (PDF) invited
    paper, most popular TSLDM article since September 2017
  26. J. Knechtel, E. F. Y. Young, and J. Lienig, “Planning Massive Interconnects in 3D Chips,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 11, pp. 1808-1821, 2015 (DOI: 10.1109/TCAD.2015.2432141) (PDF)
  27. J. Knechtel, I. L. Markov, and J. Lienig, “Assembling 2-D Blocks into 3-D Chips,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 2, pp. 228-241, 2012 (DOI: 10.1109/TCAD.2011.2174640) (PDF) most popular TCAD article in February 2012

Proceedings Papers

  1. M. Eslami, J. Knechtel, O. Sinanoglu, R. Karri, and S. Pagliarini, “Benchmarking Advanced Security Closure of Physical Layouts,” in Proc. ACM Int. Symp. Phys. Des. (ISPD), 2023. DOI: 10.1145/3569052.3578924 (PDF) M. Eslami and J. Knechtel contributed equally.
  2. S. Sreekumar, M. Ashraf, M. Nabeel, O. Sinanoglu, and J. Knechtel, “X-Volt: Joint tuning of driver strengths and supply voltages against power side-channel attacks,” in Proc. ACM Int. Symp. Phys. Des. (ISPD), 2023. DOI: 10.1145/3569052.3571882 (PDF)
  3. F. Wang, Q. Wang, B. Fu, S. Jiang, X. Zhang, L. Alrahis, O. Sinanoglu, J. Knechtel, T.-Y. Ho, and E. F. Y. Young, “Security closure of IC layouts against hardware Trojans,” in Proc. ACM Int. Symp. Phys. Des. (ISPD), 2023. DOI: 10.1145/3569052.3571878 (PDF)
  4. L. Alrahis, J. Knechtel, and O. Sinanoglu, “Graph neural networks: A powerful and versatile tool for advancing design, reliability, and security of ICs,” in Proc. IEEE/ACM Asia S. Pac. Des. Autom. Conf. (ASPDAC), invited paper, special session, 2023. DOI: 10.1145/3566097.3568345 (PDF)
  5. N. Rangarajan, S. Patnaik, M. Nabeel, M. Ashraf, S. Rai, G. Raut, H. Abunahla, B. Mohammad, S. K. Vishvakarma, A. Kumar, J. Knechtel, and O. Sinanoglu, “SCRAMBLE: A secure and configurable, memristor-based neuromorphic hardware leveraging 3D architecture,” in Proc. IEEE Comp. Soc. Ann. Symp. VLSI (ISVLSI), invited paper, special session, 2022, pp. 308–313. DOI: 10.1109/ISVLSI54635.2022.00067 (PDF)
  6. J. Knechtel, J. Gopinath, M. Ashraf, J. Bhandari, O. Sinanoglu, and R. Karri, “Benchmarking security closure of physical layouts: ISPD 2022 contest,” in Proc. ACM Int. Symp. Phys. Des. (ISPD), invited paper, 2022, pp. 221–228. DOI : 10.1145/3505170.3511046 (PDF)
  7. J. Knechtel, J. Gopinath, J. Bhandari, M. Ashraf, H. Amrouch, S. Borkar, S.-K. Lim, O. Sinanoglu, and R. Karri, “Security closure of physical layouts,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), invited paper, special session, 2021 (DOI: 10.1109/ICCAD51958.2021.9643543) (PDF)
  8. J. Lienig, S. Rothe, M. Thiele, N. Rangarajan, M. Nabeel, H. Amrouch, O. Sinanoglu, and J. Knechtel, “Toward security closure in the face of reliability effects,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), invited paper, special session, 2021 (DOI: 10.1109/ICCAD51958.2021.9643447) (PDF)
  9. J. Knechtel, “Hardware security for and beyond CMOS technology,” in Proc. ACM Int. Symp. Phys. Des. (ISPD), pp. 115-126, 2021 (DOI: 10.1145/3439706.3446902) (PDF) invited paper
  10. J. Knechtel, “Hardware security for and beyond CMOS technology: An overview on fundamentals, applications, challenges, and prospects,” in Proc. ACM Int. Symp. Phys. Des. (ISPD), pp. 75-86, 2020 (DOI: 10.1145/3372780.3378175) (PDF) invited paper
  11. J. Knechtel, E. B. Kavun, F. Regazzoni, A. Heuser, A. Chattopadhyay, D. Mukhopadhyay, S. Dey, Y. Fei, Y. Belenky, I. Levi, T. Güneysu, P. Schaumont, and I. Polian, “Towards secure composition of integrated circuits and electronic systems: On the role of EDA,” in Proc. EDAA/ACM/IEEE Des. Autom. Test Eur. (DATE), pp. 508-513, 2020 (DOI: 10.23919/DATE48585.2020.9116483) (PDF) invited paper, special session
  12. J. Knechtel, S. Patnaik, and O. Sinanoglu, “3D Integration: Another Dimension Toward Hardware Security,” in Proc. Int. On-Line Test Symp. (IOLTS), pp. 147-150, 2019 (DOI: 10.1109/IOLTS.2019.8854395) (PDF) invited paper, special session
  13. H. Li, S. Patnaik, A. Sengupta, H. Yang, J. Knechtel, B. Yu, E. F. Y. Young, and O. Sinanoglu, “Attacking split manufacturing from a deep learning perspective,” in Proc. Design Automation Conference (DAC), pp. 135:1-135:6, 2019 (DOI: 10.1145/3316781.3317780) (PDF) J. Knechtel, B. Yu, E. F. Y. Young, and O. Sinanoglu contributed equally.
  14. A. Sengupta, M. Nabeel, J. Knechtel, and O. Sinanoglu, “A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL,” in Proc. Design Automation and Test in Europe (DATE), pp. 414-419, 2019 (DOI: 10.23919/DATE.2019.8715281) (PDF)
  15. J. Knechtel, S. Patnaik, and O. Sinanoglu, “Protect Your Chip Design Intellectual Property: An Overview,” in Proc. International Conference on Omni-layer Intelligent Systems (COINS), pp. 21-216, 2019 (DOI: 10.1145/3312614.3312657) (PDF) J. Knechtel and S. Patnaik contributed equally. invited paper, special session 
  16. S. Patnaik, M. Ashraf, O. Sinanoglu, and J. Knechtel, “Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs,” in Proc. International Conference On Computer Aided Design (ICCAD), pp. 8:1-8:8, 2018 (DOI: 10.1145/3240765.3240784) (PDF)
  17. S. Patnaik, M. Ashraf, J. Knechtel, and O. Sinanoglu, “Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL,”  in Proc. Design Automation Conference (DAC), pp. 140:1-140:6, 2018 (DOI: 10.1145/3195970.3196100) (PDF)
  18. S. Patnaik, N. Rangarajan, J. Knechtel, O. Sinanoglu, and S. Rakheja, “Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices,” in Proc. Design Automation and Test in Europe (DATE), pp. 97-102, 2018 (DOI: 10.23919/DATE.2018.8341986) (PDF) S. Patnaik and N. Rangarajan contributed equally.
  19. S. Patnaik, M. Ashraf, J. Knechtel, and O. Sinanoglu, “Efficient Protection of Design IP: Disguising the Interconnects,” Interactive presentation, University Booth of Design Automation and Test in Europe (DATE), 2018 (PDF)
  20. S. Patnaik, J. Knechtel, M. Ashraf, and O. Sinanoglu, “Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing,” in Proc. Asia South Pacific Design Automation Conference (ASPDAC), pp. 251-258, 2018 (DOI: 10.1109/ASPDAC.2018.8297314) (PDF)
  21. S. Osmolovskyi, J. Knechtel, I. L. Markov, and J. Lienig, “Optimal Die Placement for Interposer-Based 3D ICs,” in Proc. Asia South Pacific Design Automation Conference (ASPDAC), pp. 513-520, 2018 (DOI: 10.1109/ASPDAC.2018.8297375) (PDF)
  22. A. Sengupta, S. Patnaik, J. Knechtel, M. Ashraf, S. Garg, and O. Sinanoglu, “Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques,” in Proc. International Conference On Computer Aided Design (ICCAD), pp. 329-336, 2017 (DOI: 10.1109/ICCAD.2017.8203796) (PDF) A. Sengupta and S. Patnaik contributed equally.
  23. S. Patnaik, M. Ashraf, J. Knechtel, and O. Sinanoglu, “Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging,” in Proc. International Conference On Computer Aided Design (ICCAD), pp. 41-48, 2017 (DOI: 10.1109/ICCAD.2017.8203758) (PDF)
  24. J. Knechtel and O. Sinanoglu, “On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity,” in Proc. Design Automation Conference (DAC), pp. 12:1-12:6, 2017 (DOI: 10.1145/3061639.3062293) (PDF)
  25. J. Knechtel and J. Lienig, “Physical Design Automation for 3D Chip Stacks – Challenges and Solutions,” in Proc. International Symposium on Physical Design (ISPD), pp. 33-40, 2016 (DOI: 10.1145/2872334.2872335) (PDF) invited paper
  26. J. Knechtel, E. F. Y. Young, and J. Lienig, “Structural Planning of 3D-IC Interconnects by Block Alignment,” in Proc. Asia South Pacific Design Automation Conference (ASPDAC), pp. 53-60, 2014 (DOI: 10.1109/ASPDAC.2014.6742866) (PDF)
  27. J. Knechtel, J. Lienig, and S. Osmolovskyi, “3D-Floorplanning für hochparallele Verbindungsstrukturen,” in Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS), pp. 16-20, 2014 (PDF) in German
  28. P. Budhathoki, J. Knechtel, A. Henschel, and I. Elfadel, “Integration of Thermal Management and Floorplanning Based on Three-Dimensional Layout Representations,” in Proc. International Conference on Electronics, Circuits, and Systems (ICECS), pp. 962-965, 2013 (DOI: 10.1109/ICECS.2013.6815572) (PDF)
  29. R. Fischbach, J. Knechtel, and J. Lienig, “Utilizing 2D and 3D Rectilinear Blocks for Efficient IP Reuse and Floorplanning of 3D-Integrated Systems,” in Proc. International Symposium on Physical Design (ISPD), pp. 11-16, 2013 (DOI: 10.1145/2451916.2451921) (PDF)
  30. J. Knechtel, M. Thiele, and J. Lienig, “Multikriterielle Layoutoptimierung durch TSV- und Deadspace-Planung für den 3D-IC-Entwurf,” in Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS), pp. 50-56, 2013 (PDF) in German
  31. J. Knechtel, I. L. Markov, J. Lienig, and M. Thiele, “Multiobjective Optimization of Deadspace, a Critical Resource for 3D-IC Integration,” in Proc. International Conference on Computer-Aided Design (ICCAD), pp. 705-712, 2012 (DOI: 10.1145/2429384.2429538) (PDF)
  32. R. Fischbach, J. Lienig, and J. Knechtel, “Investigating Modern Layout Representations for Improved 3D Design Automation,” in Proc. Great Lakes Symposium on VLSI (GLSVLSI), pp. 337-342, 2011 (DOI: 10.1145/1973009.1973076) (PDF)
  33. J. Knechtel and J. Lienig, “Eine Methodik zur Nutzung von klassischen IP-Blöcken in 3D-Schaltkreisen,” in Proc. edaWorkshop 11, pp. 45-50, 2011 (Link) in German
  34. J. Knechtel, I. L. Markov, J. Lienig, “Assembling 2D Blocks into 3D Chips,” in Proc. International Symposium on Physical Design (ISPD), pp. 81-88, 2011 (DOI: 10.1145/1960397.1960417) (PDF)

Book Chapters and Monographs

  1. N. Rangarajan, S. Patnaik, J. Knechtel, S. Rakheja, and O. Sinanoglu, “The Next Era in Hardware Security: A Perspective on Emerging Technologies for Secure Electronics,” Springer, 2022, ISBN : 978-3-030-85791-2 (DOI: 10.1007/978-3-030-85792-9) (Link)
  2. P. Budhathoki, J. Knechtel, A. Henschel, and I. A. M. Elfadel, “Integrating 3D Floorplanning and Optimization of Thermal Through-Silicon Vias,” in 3D Stacked Chips – From Emerging Processes to Heterogeneous Systems, I. A. M. Elfadel, G. Fettweis (eds.), Springer, ISBN 978-3-319-20480-2, 2016 (DOI: 10.1007/978-3-319-20481-9_10) (Link)
  3. J. Knechtel, J. Lienig, and C. C. N. Sze, “Challenges and Future Directions of 3D Physical Design,” in Physical Design for 3D Integrated Circuits., A. Todri-Sanial, C. S. Tan (eds.), CRC Press, ISBN 978-1-498-71036-7, pp. 357-386, 2015 (DOI: 10.1201/b19225) (Link)
  4. J. Knechtel, “Interconnect Planning for Physical Design of 3D Integrated Circuits,” PhD dissertation, in Fortschritt-Berichte VDI Reihe 20 Nr. 445, VDI-Verlag Düsseldorf, ISBN 978-3-18-345520-1, ISSN 0178-9473, 2014 (Link to hardcopy, Citable link to softcopy)
  5. J. Knechtel, “Nutzung von klassischen IP-Blöcken in 3D-Schaltkreisen,” in Entwurf integrierter 3D-Systeme der Elektronik, J. Lienig and M. Dietrich (eds.), Springer Vieweg Verlag, ISBN 978-3-642-30572-6, pp. 145-174, 2012 (DOI: 10.1007/978-3-642-30572-6_9) (Link) in German 2.5k downloads as of June 2019

Exclusive Preprints

  1. S. Elsharief, L. Alrahis, J. Knechtel, and O. Sinanoglu, “IsoLock: Thwarting link-prediction attacks on routing obfuscation by graph isomorphism,” Crypt. ePrint Arch., 2022. (Link)
  2. T. Mandal, G. Chacon, J. Knechtel, O. Sinanoglu, P. Gratz, and V. Soteriou, “Interposer-based root of trust,” arXiv: 2105.02917, 2021
  3. M. Nabeel, M. Ashraf, S. Patnaik, V. Soteriou, O. Sinanoglu, and J. Knechtel, “An interposer-based root of trust: Seize the opportunity for secure system-level integration of untrusted chiplets,” arXiv:1906.02044, 2019

Invited Presentation, Moderation, Organization

  • Lead organizer of 6-months long contest on advanced security closure of physical layouts at ISPD 2023 (Website)
  • Presenter, 0.75h presentation of invited paper “Benchmarking advanced security closure of physical layouts: ISPD 2023 contest” at ACM Int. Symp. Phys. Des. (ISPD), Virtual Conference, March 2023 (Slides, Recording)
  • Lead organizer of 6-months long contest on security closure of physical layouts at ISPD 2022 (Website)
  • Presenter, 0.75h presentation of invited paper “Benchmarking security closure of physical layouts: ISPD 2022 contest” at ACM Int. Symp. Phys. Des. (ISPD), Virtual Conference, March 2022 (Slides)
  • Presenter, 0.33h presentation of invited paper “Hardware security for and beyond CMOS technology” at ACM Int. Symp. Phys. Des. (ISPD), Virtual Conference, March 2021 (Slides, Recording)
  • Presenter, 0.75h invited seminar “Hardware security for and beyond CMOS technology” virtually at CESG, Texas A&M, Oct 2, 2020 (Slides)
  • Presenter, 0.5h presentation of invited paper “Towards secure composition of integrated circuits and electronic systems: On the role of EDA” within 1.5h special session “Secure Composition of Hardware Systems” at EDAA/ACM/IEEE Des. Autom. Test Eur. (DATE), Virtual Conference, April–Mai, 2020 (Slides, Recording)
  • Presenter, 0.33h presentation of invited paper “3D integration: Another dimension toward hardware security” within 1h special session “Hardware Security for Emerging Applications” at IEEE Int. On-Line Test Symp. (IOLTS), July 2, 2019, Rhodos, Greece (Slides)
  • Moderator and Presenter, moderation of 1.5h special session “Hardware Security” and 0.5h presentation of invited paper “Protect your chip design intellectual property: An overview” at ACM Int. Conf. Omni-Layer Intell. Syst. (COINS), May 6, 2019, Heraklion, Greece (Slides)
  • Presenter, 1h invited seminar, in German, “Hardware Security: Sicherheit und Schutz von elektronischen 2D- und 3D-Schaltkreisen” at FG Layoutentwurf, Fraunhofer IIS-EAS, March 19, 2018, Dresden, Germany
  • Presenter, 1h invited colloquium, in German, “Hardware Security: Eine Einführung zu Sicherheit und Schutz von elektronischen Schaltkreisen” at Institute of Electromechanical and Electronic Design, TUD, March 16, 2018, Dresden, Germany
  • Co-Organizer and Presenter, 2.5 hours tutorial session “Design Automation for 3D Chip Stacks: Challenges and Solutions” at IEEE Int. Conf. Comput. Des. (ICCD), October 2, 2016, Phoenix, AZ, USA (Slides)
  • Presenter, 0.5h presentation of invited paper “Physical design automation for 3D chip stacks – Challenges and solutions” at ACM Int. Symp. Phys. Des. (ISPD), April 4, 2016, Santa Rosa, CA, USA (Slides)

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