Last updated: Nov 9th 2021
Securing modern electronics is an important but tough challenge that requires efforts all the way from software applications down to the hardware. For the design, manufacturing, and deployment of integrated circuits (ICs), there are numerous companies and partners involved within complex and world-wide supply chains — ICs run through many hands, where some of those may be acting with malicious intent. Furthermore, once ICs are deployed in the field, an even larger attack surface arises.
This contest is part of the International Symposium on Physical Design (ISPD) 2022. Participants of this newly introduced competition theme will focus on the final frontier for securing modern electronics — the physical layout of ICs. Acting as security engineers, participants will iteratively and proactively evaluate and fix the vulnerabilities of IC layouts at design-time against different, selected threats. This competition will be open to students (undergrads, graduates, and/or post-graduates) as well as industry practitioners around the world, but prizes are limited to academic participants.
Participating teams will work on commercial or academic CAD tools of their choice, with extensive scripting or programming of the tools. The teams will be provided some example layouts and results for risk assessment, as warm-up after the announcement. The alpha round will then ask the teams to develop their defense techniques and evaluate on openly provided benchmarks, using a provided evaluation platform. Before moving to the final round, intermediate results will be published, to encourage the competition. The final round’s results will be disseminated at ISPD. The benchmarks and evaluation platform will be disseminated further after the contest, to provide a reference framework for the community on this new and exciting topic for physical design.