CAD tools traditionally optimize for PPA. However, considering that various and serious threats are emerging, future CAD flows should also incorporate techniques for secure IC design. This contest is part of ISPD and is focused on security closure of physical layouts in particular, that is, on hardening the physical layouts against various threats.
This topic is important for multiple reasons. First, many threats, like Trojan insertion or side-channel attacks, are directly targeting vulnerabilities of the physical layouts. Second, threats that are not mitigated during design-time are almost impossible to fix later on; ICs are unlike patchable software. Third, even if efforts are taken toward secure IC design at higher abstraction layers, like high-level synthesis or logic synthesis, such efforts may be undermined by, e.g., PPA optimization, thus becoming futile without dedicated support for security closure at layout level.
Participating teams will be provided early on with the problem description as well as simple example benchmarks and evaluation scripts. There will be an alpha submission phase, using further example benchmarks, with feedback provided and intermediate results published online. There will be a final submission phase on other benchmarks for final judging. Cash prizes will be awarded to the top three teams. Top teams are also encouraged to share their results further to the community, but that is not a requirement for participation. The benchmarks and evaluation platform will be disseminated at ISPD, to provide a reference for the community looking into advancing this new and exciting topic for physical design even after the contest.
See the Description page for more details.