Workshop program is now available!
Current semiconductor scaling trends indicate that in future technology nodes, a significant fraction of the chip would have to be kept powered off to meet peak power and thermal constraints. This is referred to as the dark silicon problem. The dark silicon problem introduces new challenges for EDA, low-power design and micro-architecture research across design abstractions (ranging from devices and circuits to micro-architecture and the system level). In particular, how to best utilize the abundance of (potentially dark) transistors, both in terms of design time provisioning and run-time management, so as to improve quality metrics (performance, reliability, lifetime, etc.) within peak power and thermal constraints. Indeed, dark Silicon processors are envisaged to be designed different from the largely homogeneous multi-cores commercially available today and will instead feature a heterogeneous mix of computing and communication resources to achieve higher performance and better power/energy/thermal efficiency. This workshop is intended to be a forum to synthesize emerging perspectives and research directions on the dark silicon problem from across industry and academia.
Workshop Details
The workshop is co-located with the IEEE/ACM International Conference on Computer Aided Design. The workshop will feature both invited talks from leaders in academia and industry, and a poster session for researchers to discuss and get feedback on emerging ideas. Please see the Call for Abstract Submissions for more details.
Important Dates
- Deadline for Abstract Submission:
September 25October 2nd, 2015 (Call for Abstract Submissions) - Acceptance Notification:
October 1October 4th 2015 - Workshop Date: Thursday 5th November 2015 @ Doubletree Hotel, Austin Texas.
Organizers
Muhammad Shafique, Karlsruhe Institute of Technology, Germany
Mustafa Ozdal, Bilkent University, Turkey
Siddharth Garg, New York University, USA
Gi-Joon Nam, IBM, US