HACK@DAC: The DAC 2017 Hardware Security Contest
Globalization of Integrated Circuit (IC) design is making designers and users of IC and Intellectual Property (IP) re-assess their trust in hardware. As the IC design flow spans the globe—driven by cost-conscious consumer electronics—hardware is increasingly prone to side channel analysis, reverse engineering, IP piracy, IC counterfeiting, and malicious modifications (i.e. hardware trojans). The semiconductor industry routinely loses over $4 billion annually due to one or more of these attacks.
Participating teams in this contest try to mimic the behavior of a malicious or secure-unaware CAD engineer. Their objective is to show that reasonable modifications to CAD algorithms can have unintended security consequences. They are free to use any open-source EDA tools of their choosing (but no industrial tools). The choice of EDA tools will depend on what sort of vulnerability their team seeks to create, as many attacks can be demonstrated without having a complete flow from HDL to GDSII.
Teams can evaluate their manipulations using any publicly available EDA benchmark suites including ISCAS85/89 and IWLS, among others. Freedom to choose tools and benchmarks is intended to minimize barrier of entry for teams, and to allow each open source tool to be used with the benchmarks that are native to its community.
The two examples below illustrate the kinds of vulnerabilities that might be exposed by conventional CAD tools. This is by no means an exhaustive list and we encourage you to be creative in discovering your own vulnerabilities (or building on those below).
- Consider a design generated using a logic-synthesis tool. The tool has synthesized the design such that its power consumption has been minimized. Does this optimization render the design vulnerable to power side-channel attacks? For more, see Paul C. Kocher, Joshua Jaffe, and Benjamin, “Differential Power Analysis,” in Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology, Springer-Verlag, 388-397, Jun. 1999.
- Consider a layout generated using a physical-synthesis tool to minimize the wirelength. If this design is subject to split fabrication, is it now more vulnerable to proximity attack? For more, see: Yujie Wang, Pu Chen, Jiang Hu, and Jeyavijayan (JV) Rajendran, “The cat and mouse in split manufacturing,” in Proceedings of the 53rd Annual Design Automation Conference, Pages 165:1-165:6, 2016.
Judging Criteria for Abstracts
Judging will comprise two phases. The first phase is based a two page extended abstract that outlines a proposed direction of study. No results are submitted at this stage. The submissions will be scored by a committee of judges along the five dimensions shown below.
- Overall Impression: how well written is the submission. Do the authors have ideas of what specific tools, benchmarks, and metrics they may use. This score comes with reviewer comments.
- Feasibility of Approach: does the submission convince reviewers that the proposed approach may succeed?
- Novelty: how novel and creative are the ideas, relative to what is known in public literature?
- Potential Impact: how devastating is the security vulnerability arising from this approach?
- Subtlety: To what extent are the security vulnerabilities likely to go unnoticed and make it into deployed products?
Poster Presentations at DAC
After the abstract submission, teams will have the chance to carry out their proposed experiments and present the results in a booth at DAC. First round submissions with the highest total scores will be offered grants to help support this travel*. The top teams from the DAC will be invited to expand their submission into a four page paper for a special session of a journal*.
- Team registration deadline:
March 31, 2017, 23:59 PST[Extended to April 27 Along with Abstract Submission]
- Abstract submission deadline:
April 14, 2017, 23:59 PSTApril 27, 2017, 23:59 PST (submission link)
- Finalists announced:
April 30, 2017, 23:59 PST
- Poster presentation @ DAC: June 18–June 22, 2017
Siddharth Garg, NYU
Dan Holcomb, UMass Amherst
JV Rajendran, UT Dallas