I am a PhD student at NYU and I am advised by Prof. Ramesh Karri and Prof. Mihalis Maniatakos.

Research Interests: Hardware Security, Hardware Architectures, Fully Homomorphic Encryption, Ring Processing Unit, Design-Space Exploration of Post-Quantum Cryptographic Algorithms, and Applied Cryptography.

As a PhD student, I have focused on hardware implementation and evaluation of Fully Homomorphic Encryption (FHE)  algorithms. I have explored the design space of modular multiplier, computationally most important and complex part of the FHE. We, at NYU, have fabricated the first chip, which is a Co-processor for Fully Homomorphic Encryption Execution (CoFHEE). I have worked on hardware implementation, optimization, and evaluation of Post-Qunatum Cryptgoraphy (PQC)  algorithms. Based on this, I have published a book “Hardware Architectures for Post-Quantum Digital Signature Schemes”.

I worked as a design engineer in the semiconductor division of Samsung and SanDisk. At Samsung, I was responsible for the design and architecture of the image processing IPs such as region segmentation and Embedded CODEC. I was also responsible for communication IPs such as FFT/IFFT and Time & Frequency Deinterleaving. At Western Digital, I helped in the development of System-On-Chip (SoC) level design for the memory controller.

I completed masters from the Department of Electrical Engineering, Indian Institute of Technology, Bombay (IIT-B), India. My master’s thesis focused on developing a framework for hardware-software co-simulator and neural network implementation on an FPGA. I completed under-graduation from the Department of Electrical Engineering, M.S. University, India.